1. Field of the Invention
The present invention relates to a liquid crystal display having a drive circuit formed on one of a pair of glass base plates:.
2. Description of the Related Art
There is known an active-matrix liquid crystal display in which one of a pair of transparent glass electrode base plates for sealing liquid crystal therebetween has switching thin-film transistors formed thereon. Recently, such an active-matrix liquid crystal display in which one of the pair of the glass electrode base plates also has a drive circuit mounted thereon for driving the switching thin-film transistors has been developed.
FIG. 5 shows a prior-art drive circuit of the liquid crystal display. FIG. 6 is a timing chart showing of the drive timings of components of the drive circuit shown in FIG. 5.
Each of thin-film transistors TFT and load capacitors LC are connected in series between each of data lines L201 and L202 and a common or ground potential V.sub.COM. A gate of each thin-film transistor TFT is connected to a corresponding gate line L301 or L302. Each of the gate lines L301 and L302 is connected through an invertor IN to a scanning shift register 1. The scanning shift register 1 receives a vertical synchronizing signal .phi..sub.v and a vertical clock pulse CP.sub.v from an external circuit (not shown). The scanning shift register 1 provides horizontal scanning signals G1 and G2 to the gate lines L301 and L302 in response to the vertical synchronizing signal .phi..sub.v and the vertical clock pulse CP.sub.v to horizontally scan the gate lines L301 and L302 and turn on thin-film transistors TFT.
Flip-flops FF101 and FF102 constitute a data line shift register. A data input terminal D of the flip-flop FF101 receives a horizontal synchronizing signal .phi..sub.h. An output terminal Q of the flip-flop FF101 is connected to a data input terminal D of a subsequent flip-flop FF102 and via an invertor IN101 to a control terminal L of a latch circuit LA101. An output terminal Q of the flip-flop FF102 is connected to a data input terminal of a subsequent flip-flop (not shown) and via an invertor IN102 to a control terminal L of a latch circuit LA102. A clock terminal of each of the flip-flops FF101 and FF102 receives a horizontal clock pulse CP.sub.h. Input terminals I of the latch circuits LA101 and LA102 are connected to an output terminal of an exclusive NOR circuit ENOR. Respective input terminals of the exclusive NOR circuit ENOR receive frame signals FRM and video signals DATA. An output terminal 0 of the latch circuit LA101 is connected to the data line L201. An output terminal 0 of the latch circuit LA102 is connected to the data line L202.
The flip-flops FF101 and FF102 of the data line shift register sequentially transmit the horizontal synchronizing signal .phi..sub.h on the horizontal clock pulse CP.sub.h and provide it to the control terminals L of the latch circuits LA101 and LA102 via the invertors IN101 and IN102. The input terminals I of the latch circuits LA101 and LA102 receive exclusive NOR data of the frame signals FRM and the video signals DATA. The latch circuits LA101 and LA102 sequentially receive and latch the exclusive NOR data of the frame signals FRM and the video signals DATA in response to control synchronization signals provided to the control terminals L thereof and then output the exclusive NOR data to the data lines L201 and L202. Every time the latch circuits LA101 and L102 for a single scanning line have received and latched the exclusive NOR data, the scanning shift register 1 sequentially provides the horizontal scanning signals G1 and G2 to the gate lines L301 and L302 to select thin-film transistors TFT and cause corresponding pixel capacitors LC to store signal charges via the selected thin-film transistors TFT.
In the above-described drive circuit, the horizontal scanning signals G1 and G2, as shown in the timing chart of FIG. 6, open the gates of the thin-film transistors TFT after the latch circuits LA101 and LA102 of the single scanning line have received the video signals DATA. That is, the opening of the gates of the thin-film transistors TFT is shifted in timing from a transfer of the video signals DATA. As well known, the carrier mobility of a thin-film transistor is far lower than that of a single crystal transistor. Therefore, it is difficult to provide multistage flip-flops when a drive circuit of the liquid crystal display comprises thin-film transistors. In other words, it is difficult to increase the definition of the display screen.